Hardware Description Languages for FPGA Design Coursera Quiz Answers 2022 | All Weeks Assessment Answers[Latest Update!!]

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Here, you will find Hardware Description Languages for FPGA Design Exam Answers in Bold Color which are given below.

These answers are updated recently and are 100% correct✅ answers of all week, assessment, and final exam answers of Hardware Description Languages for FPGA Design from Coursera Free Certification Course.

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About Hardware Description Languages for FPGA Design Course

This class is also offered for academic credit at the University of Colorado Boulder as ECEA 5361, which is a requirement for the Master of Science in Electrical Engineering degree.

Students will be able to design circuits using VHDL and Verilog, which are now the two most common design approaches for FPGA Design, thanks to the course Hardware Description Languages for Logic Design. It makes use of natural learning mechanisms to simplify the process of learning new languages. The presentation begins with some straightforward examples, then moves on to language rules and syntax, then moves on to more complicated examples, and eventually uses test bench simulations to validate whether or not the designs are accurate. The lecture sessions are reinforced with a large number of programming example problems in order to facilitate the acquisition of language skills. After finishing this course, each student will not only have a fundamental fluency in both languages, but also enough information to continue learning and growing skill in Verilog and VHDL on their own. This is the most essential takeaway from the experience.

Course Apply Link – Hardware Description Languages for FPGA Design

Hardware Description Languages for FPGA Design Quiz Answers

Week 1

Quiz 1: VHDL Find the Code Errors

Q1. Determine which lines have syntax errors in the accompanying VHDL code:

Select only the line numbers in which errors occur. You should find about 8-10 errors.

  • Error in Line 1
  • Error in Line 2
  • Error in Line 3
  • Error in Line 4
  • Error in Line 5
  • Error in Line 6
  • Error in Line 7
  • Error in Line 8
  • Error in Line 9
  • Error in Line 10
  • Error in Line 11
  • Error in LIne 12
  • Error in Line 13
  • Error in Line 14
  • Error in Line 15
  • Error in Line 16
  • Error in Line 17
  • Error in Line 18
  • Error in Line 19
  • Error in Line 20

Quiz 2: Module 1 Quiz

Q1. Name the parts of a VHDL file?

  • Entity and Architecture pair
  • Library, Entity, and Architecture
  • Entity input, output, and Architecture process
  • Module, Sensitivity list, and Signals

Q2. The V in VHDL stands for?

  • Very
  • Verilog
  • Very High Speed IC
  • Version 5 (V) of Hardware Description Language

Q3. The VHDL variable assignment operator := has:

  • Current value
  • Future value
  • Previous value
  • All of the above

Q4. The following VHDL signals are equivalent:

  • D(1), d(2)
  • DATA_in : std_logic, data_IN : std_logic
  • string “abc”, string “123”
  • X : INTEGER, Y : REAL

Q5. The library for VHDL std_logic type includes the values of:

U X 0 1 Z W L H – If the function truth table for “not” function is : not ‘1’ = ‘0’,

please provide : not ‘X’ = ?

  • ‘0’
  • ‘1’
  • ‘Z’
  • ‘X’

Q6. In the FPGA design flow, Timing based simulation occurs:

Before synthesis and placement of logic

After synthesis and placement of logic

Q7. If A = “1010”, using the shift left logical, Provide ? <= A SLL 2

  • “1011”
  • “1000”
  • “1010”
  • “0010”

Q8. Which one of the following statements is correct about VHDL signals? (Mark all that apply)

  • Signals can be defined within entity block.
  • Signals connected to ports must have the same “mode specifier”. (i.e. in, out, inout, …)
  • Signals can be used in both concurrent assignments and in sequential blocks.
  • A signal changes its value at the “same time” at the next scheduled event after the signal assignment expression is evaluated.

Q9. VHDL can be implemented into the following devices:

  • FPGA
  • ASIC
  • CPLD
  • All of the above

Q10. Types of VHDL port Declarations in the Entity:

  • generics
  • signals
  • input, output, inout
  • in, out, inout

Also Read these Articles:

Week 2

Quiz 1: Module 2 Quiz

Q1. In VHDL the following assignment statements operate in parallel:

Y <= A + B;

Z <= Y – C;

  • From assignment to assignment within a process
  • From process to process within an architecture
  • From port to port within an entity

Q2. In the following VHDL architecture code:

begin

with SEL select

z <= A when “00”,

B when “01”,

C when “10”,

D when others;

end

The when others covers and catches the following conditions:

  • D when “11”,
  • D when “00”,
  • D when “UU”,
  • D when “X0”,

Q3. Choose the VHDL architecture signal assignment for a selected 2:1 MUX:

  • begin
    • with SEL select
    • Z_out <= A_in when ‘0’,
    • B_in when others;
    • end sel_arch;
  • begin mux_proc: process (A_in, B_in, SEL, Z_out)
    • begin
    • if SEL = ‘0’ then Z_out <= A_in;
    • else Z_out <= B_in;
    • end if;
    • end process mux_proc;
  • begin
    • Z_out <= A_in when SEL = ‘0’ else
    • B_in;
    • end;
  • begin
    • with SEL select
    • Z_out <= A_in when ‘0’;
    • else B_in;
    • end sel_arch;

Q4. In the code below, which statement is correct regarding the concatenation assignment?

entity bus_build is port (

A: in std_logic_vector(3 downto 0);

Z: out std_logic_vector(7 downto 0) );

end entity bus_build;

architecture bus_arch of bus_build is

begin bus_proc: process (A) begin

Z <= “000” & A & ‘1’; — This is the Bus Concatenation

end process bus_proc;

end architecture bus_arch;

  • we cannot combine signals with different width
  • Adding ‘1’ is illegal in this assignment
  • Z has to be exactly 8 bits otherwise there will be an error.
  • Z can be wider than the result of concatenation operation in terms of bit-width.

Q5. An unintended Latch is generated from the following VHDL code, because … ?

begin latch_proc: process(clock, data)

begin

if ( rising_edge(clock) ) then

q <= data;

end if;

end process latch_proc;

  • clock is included in the sensitivity list
  • data is included in the sensitivity list
  • clock is a synchronous process
  • there is no else statement for data

Q6. Which of the following statements are correct about state machines? (Mark all that apply)

  • Gray encoding technique consumes more logic cells than other encoding methods
  • One-Hot encoding results in the greatest number of logic cells among other encoding methods.
  • In Johnson encoding there will be more than one bit transitioning from one state to the immediate next one.
  • Binary encoding is the most efficient way to implement state machines in terms of number of logic cells.

Q7. In the following VHDL snippet, select all correct answers:

Constant T = 10: time:= 20ns; — clock period

process begin

clock <= ‘0’;

wait for T/2;

clock <=’1’;

wait for T/2;

end process;

z_out <= A_bus and B_bus after 2ns;

  • 2ns is synthesized into the design
  • Delays can only be used in simulation.
  • A clock signal with period of 20 ns will be synthesized in the FPGA fabric.
  • The value of T cannot be changed inside the process block

Q8. The following VHDL statements infer a flip-flop: (Mark all that apply)

  • if (clk = ‘1’) then q <= d;
  • if (rising_edge (clk) ) then q <= d;
  • if ( clk’event and clk=’1′) then q<=d;
  • q <= d when (sel = ‘1’) else ‘0’;

Q9. choose which VHDL assignments create a flip-flop: (Mark all that apply)

if (rising_edge(clk) ) then

X <= A and B;

Y:= C nand D;

Z <= E or F;

end if;

  • X
  • Y
  • Z

Q10. The following VHDL code generates a divided half clock:

  • process (clk) begin
    • if ( rising_edge(clk) ) then q <= div2 clk;
    • end if;
    • end process;
  • process (clk) begin
    • if ( rising_edge(clk) ) then q <= not d;
    • end if;
    • end process;

Week 3

Quiz 1: Verilog Find the Errors

Q1. Determine which lines have syntax errors in the accompanying Verilog code. There are at least 10 errorsUv269eeWSPC9uvXnlhjwYw 3588c4f5f6642eb4f735cab0da6dff95 AAC2M3P2

Select only the lines below which have errors in the code listed above.

  • Error in line 1
  • Error in line 2
  • Error in line 3
  • Error in line 4
  • Error in line 5
  • Error in line 6
  • Error in line 7
  • Error in line 8
  • Error in line 9
  • Error in line 10
  • Error in line 11
  • Error in line 12
  • Error in line 13
  • Error in line 14
  • Error in line 15
  • Error in line 16
  • Error in line 17
  • Error in line 18
  • Error in line 19
  • Error in line 20
  • Error in line 21

Quiz 2: Module 3 Quiz

Q1. Which of the following methods is a Verilog modeling styles? (Mark all that apply)

  • Structural (gate-level)
  • instantiated (instance units)
  • behavioral (always)
  • dataflow (assign)

Q2. Which of the following statements is correct? (Mark all that apply)

  • Combinatorial logic circuits require a clock edge to operate?
  • “Net” data type must be driven continuously.
  • “Register” datatypes includes “tri” and “reg” .
  • ‘Nets” datatypes are used to wire up instantiations.

Q3. Which of the following statements is correct in Verilog? (Mark all that apply)

  • Integer datatype represents general-purpose variables.
  • Implicitly declared “reg” types can store unsigned numbers.
  • “reg” can be modeled as a wire or as a storage.
  • “reg” is a short form for ‘register’

Q4. Verilog supports the following logic values: x, z, 0, 1. An FPGA I/O will measure the following values by a voltmeter:

  • Logic value 0: Voltmeter 0.0V.
  • Logic value x: Voltmeter 2.5V.
  • Logic value 1: Voltmeter 2.5V.
  • Logic value z: Voltmeter 2.5V.

Q5. Blocking assignments in verilog ( = ) execute in series in an always block.

  • = assignments operate in parallel
  • = assignments operate in series.

Q6. If Z_out = 3’b101 the using the replication operator {2{Z_out}} creates:

  • 1010
  • 101101

Q7. Which of the following statements is correct in Verilog? (Mark all that apply)

  • Combinatorial circuits should include all inputs for the circuit in the sensitivity list:
  • “assign” statement must be used in a sequential block (begin … end)
  • When using port names in module instantiation, one shall be careful about order of the ports.
  • Blocking or non-blocking assignments can be used in sequential blocks.

Q8. Select all correct statements:

  • Since verilog is not case sensitive, the following statements are equivalent:
    • C_IN = A;
    • c_in = A;
  • “Time” is a datatype and is not supported for synthesis.
  • “===” is the case equality operator and is not synthesizable
  • The following assignments are equal:
    • assign y = ( a | b ) & ~c;
    • assign y = a | b & ~c;

Q9. Select all the correct answers from the following statements:

  • Verilog uses a positional or ordered port list for instances, so the following ordered port lists are equivalent:
    • add4 unit_1 (a, b, c_in, c_out, sum);
    • add4 unit_2 (a, b, c_out, c_in, sum);
  • supply0 and supply1 are data types representing ground and power respectively
  • When connecting modules, inputs can be Nets or Registers, outputs must be Nets (wire, etc.)
  • The left-hand-side (LHS) of procedural assignments must be of a Register type.

Q10. reg [31:0] my_data;

assign my_data = 16’hCAFE;

The reg my_data has the 32 bit value as:

  • my_data = 0000_CAFE
  • my_data = FFFF_CAFE
  • my_data = XXXX_CAFE

Week 4

Quiz 1: Module 4 Quiz

Q1. In Verilog, a latch is generated from the following code, because … :

always @(clock or d_in or clear)

begin

if (clear == 1) q_out <= 0;

else if (clock == 1) q_out <= d_in;

end

  • Because clear is an asynchronous reset.
  • Because d_in is included in the sensitivity list.
  • Because clock is synchronous.

Q2. The following verilog code has a synchronous reset, because … :

always @(posedge clk)

begin

if ( ! reset ) Q <= 4’b0000;

else if (shift == 1) Q <= Q << 1;

end

  • Q output is shifted by one with the << shift operator.
  • reset is inverted by ! whenever reset is evaluated.
  • reset is evaluated within the posedge clk block.

Q3. Select the incomplete sensitivity list item for the combinatorial circuit causing indeterminate synthesis and simulation results:

  • always @ (a, b, c) y = a & b & c;
  • always @ (a or b) y = a & b & c;
  • always @ * y = a & b & c:

Q4. The following verilog code generates a:

module my_block (

input wire clock, reset,

input wire [15:0] d,

output reg [15:0] q );

always @ (posedge clock, negedge reset)

if ( ! reset ) q <= 0;

else q <= d;

endmodule

  • Flip Flop.
  • Counter.
  • RAM Memory.
  • Register.

Q5. The following verilog code is important, because … :

assign z_out = ( oe == 1)? data_out: 8’bz;

(Select any answer that applies.)

  • IO power is reduced.
  • The z_out bus is protected, provided the output enable is timed correctly.
  • The IO is undriven, so other devices connected can safely drive.
  • The bus is MUXed so other devices on the bus can safely drive.

Q6. Select the following verilog code signal declaration for a RAM memory:

  • reg [1023:0] RAM;
  • wire [31:0] RAM [1023:0];
  • signal RAM: ram_type:= read_ram(“RAM_FILE.txt”);
  • reg [31:0] RAM [1023:0];

Q7. Recall the memory constructs and select all correct statements:

  • After Synthesis, the following ROM data can be written to for future reads.

always @*

case(addr)

2’b00: rom_data = 8’b1000_0000;

2’b01: rom_data = 8’b1010_1010;

2’b10: rom_data = 8’b0101_0101;

2’b11: rom_data = 8’b1111_0011;

endcase

  • In Verilog, the memory storage is declared by using a two-dimensional array.
  • RAM can be initialized by an external file.
  • In an FPGA, the synthesizer uses only the RAM IP block or block memory to implement RAM.

Q8. The following testbench verilog creates:

always

begin

clock = 1’b0; #(50/2);

clock = 1’b1; #(50/2);

end

  • A single pulse 50ns wide.
  • Forever repeating clock at 20MHz.
  • A single pulse 25ns wide.
  • Forever repeating clock at 50MHz.

Q9. Recall the test bench structure and select all correct answers from below:

  • Pound ‘#’ delays such as the following are synthesized into delay elements in the cell library:
    • reset = 1’b0;
    • #100;
    • reset = 1’b1;
  • Model under test uses either external stimulus or test vectors to generate output vectors.
  • Output vectors alone are enough to validate a design.
  • There is no sensitivity list present in test bench module at the top level

Q10. Assertions are used in verilog testbenches to perform the following:

(select any that are True)

  • Severity level can be set to various levels: fatal, error, warning, and info.
  • Assertions are displayed during synthesis for debug.
  • Assertions can be turned on or off during simulation run.
  • Assertions evaluate and print useful messages for design debug.

Conclusion

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